All
Search
Images
Videos
Shorts
Maps
News
More
Shopping
Flights
Travel
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
Reverse Debug with Verdi | Synopsys Inc
Jul 13, 2023
linkedin.com
1:09
IC验证工程师: Bug修不完?那就先给灵魂Debug
102 views
2 weeks ago
bilibili
大曾同学聊IC
【席老师】你知道怎么让Verdi波形显示状态机名字吗【芯片】【芯片设计
…
1.1K views
Feb 6, 2024
bilibili
芯片EDA技术席老师
12:24
UVM Simplified (#10 UVM Interface and Connections)
21.9K views
Aug 27, 2020
YouTube
ASIC Lab
Introduction to the UVM
3.1K views
Sep 15, 2014
YouTube
VerificationAcademy
[Synopsys tool 강좌] Verdi (1/3) - KDB, FSDB, GUI, Preference
6.1K views
Jan 11, 2021
YouTube
KK SystemVerilog
【新思席老师】【Verdi】verdi---how to debug glitch
2.3K views
Sep 15, 2022
bilibili
芯片EDA技术席老师
ALDEC DEMO - UVM Based Environment for Ibex RISC V CPU
…
3K views
Nov 25, 2020
YouTube
aldecinc
Writing SV UVM Testbench 01 - Design and Specification
3.1K views
Apr 24, 2023
YouTube
Open Logic
SimVision UVM Toolbar and Message Hyperlinks
3.2K views
Dec 21, 2012
YouTube
Cadence Design Systems
3:03
UVM Simplified (#3 UVM TOP)
27.9K views
Jul 29, 2020
YouTube
ASIC Lab
8:12
SimVision Assertion Debug Introduction
13.2K views
Sep 30, 2013
YouTube
Cadence Design Systems
9:11
UVM-1: UVM Basics | Synopsys
88.4K views
Dec 21, 2015
YouTube
Synopsys
24:01
First Steps with UVM Part 1
100.5K views
May 14, 2012
YouTube
Doulos Training
10:00
Introduction to UVM - The Universal Verification Methodology for Syst
…
119.7K views
Mar 29, 2011
YouTube
Doulos Training
9:08
Unleashing SystemVerilog and UVM: Introduction | Synopsys
78.8K views
Dec 21, 2015
YouTube
Synopsys
6:09
Interactive Reverse Debug in Verdi
16.3K views
Nov 25, 2016
YouTube
jonathan cheah
5:45
Interactive Debug with Verdi | Synopsys
72K views
Feb 1, 2018
YouTube
Synopsys
8:10
UVM-2: UVM Factory | Synopsys
41.8K views
Dec 21, 2015
YouTube
Synopsys
43:58
In-System Debugging with Vivado Using ILA Core
53.5K views
Jan 31, 2020
YouTube
Vipin Kizheppatt
9:51
Writing a testbench in VHDL using Xilinx Vivado Part 1 by Vincent Cla
…
8.3K views
Mar 4, 2021
YouTube
fpgabe
7:59
SV-1: Object-oriented Programming for Designers | Synopsys
47.3K views
Dec 21, 2015
YouTube
Synopsys
3:45
La La Land (2016) - A Lovely Night Scene (5/11) | Movieclips
8.2M views
Apr 11, 2018
YouTube
Movieclips
26:09
VLSI Verification Courses: Udemy : UVM in Systemverilog: Quick Star
…
12.3K views
Jul 27, 2020
YouTube
Systemverilog Academy
4:58
How to Write a SystemVerilog TestBench (SystemVerilog Tutoria
…
40.7K views
Dec 13, 2016
YouTube
Charles Clayton
6:40
AMS Co-simulation Debug with Verdi | Synopsys
6.7K views
Feb 1, 2018
YouTube
Synopsys
53:43
How to write SPI Interface code in Verilog HDL for a 12-bit ADC (usin
…
53.7K views
Sep 22, 2020
YouTube
Visual Electric
20:14
Linux Kernel debugging with Visual Studio Code
5.4K views
May 12, 2020
YouTube
Ron Munitz
5:09
Cool Things You Can Do with Verdi – Verification Planning (Advanced)
6.9K views
Mar 1, 2016
YouTube
Synopsys
11:32
How to use vivado for Beginners | Verilog code | Testbench | Schem
…
179.5K views
Jan 19, 2021
YouTube
Anand Raj
See more videos
More like this
Feedback