Design-Reuse9d
Low Power High Speed All Digital Phase Locked Loops
Phase lock begins with frequency acquisition ... Zuffetti, R.Castello , A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter, IEEE J. Solid-State Circuits, ...
Design-Reuse3y
A Digital Design Flow for Differential ECL High Speed Applications
an additional development phase is introduced within the general digital CMOS Design Flow. In this differential phase, a netlist converter analyzes the synthesized single-ended netlist and replaces ...